STM32MP135C/F 数据手册

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226页
嵌入式系统
Cortex-A7
低功耗模式
安全特性
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基于ARM Cortex-A7的STM32MP135C/F微处理器详细技术规格：低功耗与高安全性设计
This is information on a product in full production.
April 2025 DS13483 Rev 7 1/226
STM32MP135C STM32MP135F
Arm
®
Cortex
®
-A7 up to 1 GHz, LCD-TFT, camera interface, 2×ETH,
2×CAN FD, 2×ADC, 24 timers, audio, crypto and adv. security
Datasheet - production data
Features
Includes ST state-of-the-art patented
technology
Core
• 32-bit Arm
®
Cortex
®
-A7
– L1 32-Kbyte I / 32-Kbyte D
– 128-Kbyte unified level 2 cache
–Arm
®
NEON™ and Arm
®
TrustZone
®
Memories
• External DDR memory up to 1 Gbyte
– up to LPDDR2/LPDDR3-1066 16-bit
– up to DDR3/DDR3L-1066 16-bit
• 168 Kbytes of internal SRAM: 128 Kbytes of
AXI SYSRAM + 32 Kbytes of AHB SRAM and
8 Kbytes of SRAM in Backup domain
• Dual Quad-SPI memory interface
• Flexible external memory controller with up to
16-bit data bus: parallel interface to connect
external ICs and SLC NAND memories with up
to 8-bit ECC
Security/safety
• Secure boot, TrustZone
®
peripherals,
12 x tamper pins including 5 x active tampers
• Temperature, voltage, frequency and
32 kHz monitoring
Reset and power management
• 1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os)
• POR, PDR, PVD and BOR
• On-chip LDOs (USB 1.8 V, 1.1 V)
• Backup regulator (~0.9 V)
• Internal temperature sensors
• Low-power modes: Sleep, Stop, LPLV-Stop,
LPLV-Stop2 and Standby
• DDR retention in Standby mode
• Controls for PMIC companion chip
Clock management
• Internal oscillators: 64 MHz HSI oscillator,
4 MHz CSI oscillator, 32 kHz LSI oscillator
• External oscillators: 8-48 MHz HSE oscillator,
32.768 kHz LSE oscillator
• 4 × PLLs with fractional mode
General-purpose input/outputs
• Up to 135 secure I/O ports with interrupt
capability
• Up to 6 wakeup
Interconnect matrix
• 2 bus matrices
–64-bit Arm
®
AMBA
®
AXI interconnect,
up to 266 MHz
–32-bit Arm
®
AMBA
®
AHB interconnect,
up to 209 MHz
4 DMA controllers to unload the CPU
• 56 physical channels in total
• 1 x high-speed general-purpose master direct
memory access controller (MDMA)
• 3 × dual-port DMAs with FIFO and request
router capabilities for optimal peripheral
management
LFBGA
TFBGA289 (9 × 9 mm)
TFBGA320 (11 × 11 mm)
min pitch 0.5 mm
TFBGA
LFBGA289 (14 × 14mm)
Pitch 0.8 mm
www.st.com
STM32MP135C/F
2/226 DS13483 Rev 7
Up to 30 communication peripherals
• 5 × I
2
C FM+ (1 Mbit/s, SMBus/PMBus™)
• 4 x UART + 4 x USART (12.5 Mbit/s,
ISO7816 interface, LIN, IrDA, SPI)
• 5 × SPI (50 Mbit/s, including 4 with full-duplex
I
2
S audio class accuracy via internal audio PLL
or external clock)(+2 QUADSPI + 4 with
USART)
• 2 × SAI (stereo audio: I
2
S, PDM, SPDIF Tx)
• SPDIF Rx with 4 inputs
• 2 × SDMMC up to 8 bits (SD/e•MMC™/SDIO)
• 2 × CAN controllers supporting CAN FD
protocol
• 2 × USB 2.0 high-speed Host
– or 1 × USB 2.0 high-speed Host
+ 1 × USB 2.0 high-speed OTG
simultaneously
• 2 x Ethernet MAC/GMAC
– IEEE 1588v2 hardware, MII/RMII/RGMII
• 8- to 16-bit camera interface, 3 Mpix @30 fps
or 5Mpix @15 fps in color or monochrome with
pixel clock @120 MHz (max freq)
6 analog peripherals
• 2 × ADCs with 12-bit max. resolution up to
5 Msps
• 1 x temperature sensor
• 1 x digital filter for sigma-delta modulator
(DFSDM) with 4 channels and 2 filters
• Internal or external ADC reference V
REF+
Graphics
• LCD-TFT controller, up to 24-bit // RGB888
– up to WXGA (1366 × 768) @60 fps or up to
Full HD (1920 x 1080) @ 30 fps
– pixel clock up to 90 MHz
– two layers (incl. 1 secured) with
programmable color LUT
Up to 24 timers and 2 watchdogs
• 2 × 32-bit timers with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input
• 2 × 16-bit advanced timers
• 10 × 16-bit general-purpose timers (including
2 basic timers without PWM)
• 5 × 16-bit low-power timers
• Secure RTC with sub-second accuracy and
hardware calendar
• 4 Cortex
®
-A7 system timers (secure,
non-secure, virtual, hypervisor)
• 2 × independent watchdogs
Hardware acceleration
• AES 128, 192, 256 DES/TDES
• AES 128, 256 with DPA protection
• PKA ECC/RSA with DPA protection
• AES 128 on-the-fly DRAM encryption and
decryption
• HASH (SHA-1, SHA-224, SHA-256, SHA-384,
SHA-512, SHA-3), HMAC
• 1 x true random number generator (6 triple
oscillators)
• 1 x CRC calculation unit
Debug mode
• Arm
®
CoreSight™ trace and debug: SWD and
JTAG interfaces usable as GPIOs
• 4-Kbyte embedded trace buffer
3072-bit fuses including 96-bit unique ID,
up to 1280 bits available for user and
256-bit HUK to protect AES 256 keys
All packages are ECOPACK2 compliant
DS13483 Rev 7 3/226
STM32MP135C/F Contents
6
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 Arm Cortex-A7 subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.1 External SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 DDR3/DDR3L/LPDDR2/LPDDR3 controller (DDRCTRL) . . . . . . . . . . . . 21
3.4 TrustZone address space controller for DDR (TZC) . . . . . . . . . . . . . . . . 23
3.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.6 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.6.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.6.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.7 Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.8 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.8.1 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.8.2 System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.9 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.10 TrustZone protection controller (ETZPC) . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.11 Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.12 DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.13 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 31
3.14 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 31
3.15 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.16 Dual Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . 32
3.17 Analog-to-digital converters (ADC1, ADC2) . . . . . . . . . . . . . . . . . . . . . . . 32
3.18 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.19 Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Contents STM32MP135C/F
4/226 DS13483 Rev 7
3.20 V
BAT
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.21 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.22 Digital filter for sigma-delta modulator (DFSDM) . . . . . . . . . . . . . . . . . . . 34
3.23 Digital camera interface pipe processing (DCMIPP) . . . . . . . . . . . . . . . . 36
3.24 LCD-TFT display controller (LTDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.25 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.26 Cryptographic and hash processors (CRYP, SAES, PKA and HASH) . . . 37
3.27 Boot and security and OTP control (BSEC) . . . . . . . . . . . . . . . . . . . . . . . 37
3.28 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.28.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.28.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM12, TIM13,
TIM14, TIM15, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.28.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.28.4 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 40
3.28.5 Independent watchdogs (IWDG1, IWDG2) . . . . . . . . . . . . . . . . . . . . . . 40
3.28.6 Generic timers (Cortex-A7 CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.29 System timer generation (STGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.30 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.31 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.32 Inter-integrated circuit interfaces (I2C1, I2C2, I2C3, I2C4, I2C5) . . . . . . . 42
3.33 Universal synchronous asynchronous receiver transmitter
(USART1, USART2, USART3, USART6 and UART4, UART5,
UART7, UART8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.34 Serial peripheral interfaces (SPI1, SPI2, SPI3, SPI4, SPI5)
– inter- integrated sound interfaces (I2S1, I2S2, I2S3, I2S4) . . . . . . . . . . 44
3.35 Serial audio interfaces (SAI1, SAI2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.36 SPDIF receiver interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.37 Secure digital input/output MultiMediaCard interfaces
(SDMMC1, SDMMC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.38 Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 46
3.39 Universal serial bus high-speed host (USBH) . . . . . . . . . . . . . . . . . . . . . 47
3.40 USB on-the-go high-speed (OTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.41 Gigabit Ethernet MAC interfaces (ETH1, ETH2) . . . . . . . . . . . . . . . . . . . 48
3.42 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4 Pinout, pin description and alternate functions . . . . . . . . . . . . . . . . . . 50
DS13483 Rev 7 5/226
STM32MP135C/F Contents
6
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 107
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . 109
6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.5 Embedded regulators characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.3.9 External clock source security characteristics . . . . . . . . . . . . . . . . . . . 129
6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 136
6.3.13 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.3.15 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 141
6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.3.19 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.3.20 QUADSPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
6.3.21 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
6.3.22 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
6.3.23 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 181
6.3.24 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

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