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内容概要:本文档详细介绍了STM32MP23xA/D系列微控制器的主要特性和功能模块。STM32MP23xA/D采用双核架构,包括64位双核Arm Cortex-A35(最高频率1.5 GHz)和32位单核Arm Cortex-M33(最高频率400 MHz)。该系列支持多种外部存储器接口,如DDR3L、DDR4、LPDDR4,内置776-Kbyte SRAM,具备TrustZone安全技术、电源管理特性、丰富的通信外设以及低功耗模式。此外,还集成了AI加速器、3D图形处理器、视频解码器、USB 2.0接口等功能组件。文档提供了详细的内存配置、时钟管理、定时器、GPIO端口、调试接口等信息,并列出了具体的技术参数和电气特性。 适合人群:适用于嵌入式系统开发工程师、硬件设计师及相关领域的研究人员,特别是对高性能ARM架构微控制器有需求的专业人士。 使用场景及目标:① 开发需要高效处理能力的应用程序,如工业自动化、智能家居、物联网设备等;② 构建具备高安全性要求的产品,利用TrustZone技术实现数据保护;③ 设计低功耗解决方案,优化电池供电设备的续航时间;④ 实现复杂的人机交互界面,借助集成的GPU和显示控制器提升用户体验。 其他说明:STM32MP23xA/D系列微控制器以其先进的技术和丰富的外设资源,为开发者提供了一个强大的平台。文档不仅涵盖了基本的功能介绍,还包括了详细的电气规格和技术细节,帮助用户更好地理解和应用这些产品。建议使用者结合实际项目需求深入研究相关章节,并参考官方提供的参考手册和其他辅助资料进行开发。
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Features
Includes ST state-of-the-art patented technology.
Cores
• Up to 64-bit dual-core Arm
®
Cortex
®
-A35
– Up to 1.5 GHz
– 32-Kbyte I + 32-Kbyte D level 1 cache for each core
– 512-Kbyte unified level 2 cache
– Arm
®
NEON™ and Arm
®
TrustZone
®
•
32-bit Arm
®
Cortex
®
-M33 with FPU/MPU
– Up to 400 MHz
– L1 16-Kbyte I / 16-Kbyte D
–
Arm
®
TrustZone
®
Memories
• External DDR memory up to 4 Gbytes
– Up to DDR3L-2133 16-bit
– Up to DDR4-2400 16-bit
– Up to LPDDR4-2400 16-bit
• 776-Kbyte internal SRAM: 256-Kbyte AXI SYSRAM, 128-Kbyte AXI video RAM
or SYSRAM extension, 256-Kbyte AHB SRAM, 128-Kbyte AHB SRAM with
ECC in backup domain, 8-Kbyte SRAM with ECC in backup domain
• Two Octo-SPI memory interfaces
• Flexible external memory controller with up to 16-bit data bus: parallel interface
to connect external ICs, and SLC NAND memories with up to 8-bit ECC
Security/safety
• TrustZone
®
peripherals, active tamper, environmental monitors, display secure
layers, hardware accelerators
• Complete resource isolation framework
Reset and power management
• 1.71 to 1.95 V and 2.7/3.0 to 3.6 V multiple section I/O supply
• POR, PDR, PVD, and BOR
• On-chip LDO and power-switches for RETRAM, BKPSRAM, V
SW
, and
SmartRun domains
• Dedicated supplies for Cortex
®
-A35 and GPU/NPU (if present)
• Internal temperature sensors
• Low-power modes: Sleep, Stop, and Standby
• DDR memory retention in Standby mode
• Controls for PMIC companion chip
TFBGA361 (16 × 16 mm) pitch 0.8 mm
VFBGA361 (10 × 10 mm) pitch 0.5 mm
VFBGA424 (14 × 14 mm) pitch 0.5 mm
BGA
Product summary
STM32MP23xA/D
STM32MP231A,
STM32MP231D,
STM32MP233A,
STM32MP233D,
STM32MP235A,
STM32MP235D
Arm
®
based dual Cortex
®
-A35 1.5 GHz + Cortex
®
-M33 MPU, AI, 3D GPU,
video decoder, TFT/DSI/LVDS, USB 2.0
STM32MP231A/D STM32MP233A/D
STM32MP235A/D
Datasheet
DS14635 - Rev 3 - April 2025
For further information, contact your local STMicroelectronics sales office.
www.st.com

Low-power consumption
Clock management
• Internal oscillators: 64 MHz HSI, 4/16 MHz MSI, 32 kHz LSI
• External oscillators: 16-48 MHz HSE, 32.768 kHz LSE
• Up to 8× PLLs with fractional mode
General-purpose inputs/outputs
• Up to 144 secure I/O ports with interrupt capability
– Up to 6 wake-up inputs
– Up to 7 tamper input pins + 5 active tampers output pins
Interconnect matrix
• Bus matrices
– 128-, 64-, 32-bit STNoC interconnect, up to 600 MHz
–
32-bit Arm
®
AMBA
®
AHB interconnect, up to 400 MHz
3 DMA controllers to unload the CPU
• 48 physical channels in total
• 3× dual master port, high-performance, general-purpose, direct memory access controller (HPDMA), 16
channels each
Up to 39 communication peripherals
• 4× I
2
C FM+ (1 Mbit/s, SMBus/PMBus
®
)
• 3× I
3
C (12.5 Mbit/s)
• 3× UART + 4× USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI) + 1× LPUART
• 6× SPI (50 Mbit/s, including 3 with full duplex I
2
S audio class accuracy via internal audio PLL or external
clock)(+2 with OCTOSPI + 4 with USART)
• 4× SAI (stereo audio: I
2
S, PDM, SPDIF Tx)
• SPDIF Rx with 4 inputs
• 3× SDMMC up to 8-bit (SD/e•MMC™/SDIO)
• Up to 2× CAN controllers supporting CAN FD protocol, out of which one supports time-triggered CAN
(TTCAN)
• 1× USB 2.0 high-speed Host with embedded 480 Mbits/s PHY
• 1× USB 2.0 high-speed dual role data with embedded 480 Mbits/s PHY
• 1× USB Type-C
®
Power Delivery control with two CC lines PHY
• Up to 2× Gigabit Ethernet interfaces
– 1× Gigabit Ethernet GMAC with one external PHY interface (optional)
– 1× Gigabit Ethernet GMAC with one external PHY interface
– TSN, IEEE 1588v2 hardware, MII/RMII/RGMII
• Camera interface #1 (5 Mpixels at 30 fps)
– MIPI CSI-2
®
, 2× data lanes up to 2.5 Gbit/s each
– 8- to 16-bit parallel, up to 120 MHz
– RGB, YUV, JPG, RawBayer with Lite-ISP
– Lite-ISP, demosaicing, downscaling, cropping, 3 pixel pipelines
STM32MP231A/D STM32MP233A/D STM32MP235A/D
DS14635 - Rev 3
page 2/208

• Camera interface #2 (1 Mpixels at 15 fps)
– 8- to 14-bit parallel, up to 80 MHz
– RGB, YUV, JPG
– Cropping
• Digital parallel interface up to 16-bit input or output
6 analog peripherals
• 3 × ADCs with 12-bit max. resolution (up to 5 Msps each, up to 23 channels)
• Internal temperature sensor (DTS)
• 1× multifunction digital filter (MDF) with up to 4 channels/4 filters
• Internal (VREFBUF) or external ADC reference V
REF+
Graphics
•
Optional 3D GPU: VeriSilicon
®
- Up to 400 MHz
–
OpenGL
®
ES 3.1 - Vulkan 1.3
– OpenCL™ 3.0, OpenVX™ 1.3
– Up to 66.5 Mtriangle/s, 400 Mpixel/s
• LCD-TFT controller, up to 24-bit // RGB888
– Up to FHD (1920 × 1080) at 60 fps
– 3 layers including a secure layer
– YUV support, 90° output rotation
• Optional MIPI DSI
®
, 4× data lanes, up to 2.5 Gbit/s each
– Up to QXGA (2048 × 1536) at 60 fps
• Optional FPD-1 and OpenLDI JEIDA/VESA (LVDS), 4× data lanes, up to 1.1 Gbit/s per lane
– Up to FHD (1920 × 1080) at 60 fps
Artificial intelligence
• Optional NPU: VeriSilicon
®
- Up to 400 MHz
– TensorFlowLite - ONNX - Linux NN
Video processing
• Optional hardware video decoder up to 600 MHz
– H264/VP8 up to FHD (1920×1080) at 60 fps
– JPEG up to 500 Mpixel/s
– 128 Kbytes of video RAM
Up to 32 timers and 5 watchdogs
• 4× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
• 2× 16-bit advanced motor control timers
• 10× 16-bit general-purpose timers (including 2 basic timers without PWM)
• 5× 16-bit low-power timers
• Secure RTC with subsecond accuracy and hardware calendar
• Up to 2× 4 Cortex
®
-A35 system timers (secure, non-secure, virtual, hypervisor)
• 2× SysTick Cortex
®
-M33 timer (secure, non-secure)
• 5× watchdogs (4× independent and 1× window)
Hardware acceleration
• ECDSA verification with SCA
• HASH (SHA-1, SHA-224, SHA-256, SHA3), HMAC
• True random number generator
STM32MP231A/D STM32MP233A/D STM32MP235A/D
DS14635 - Rev 3
page 3/208

• CRC calculation unit
Debug mode
• Arm
®
CoreSight™ trace and debug: SWD and JTAG interfaces
12288-bit fuses including 96-bit unique ID
All packages are ECOPACK2 compliant
STM32MP231A/D STM32MP233A/D STM32MP235A/D
DS14635 - Rev 3
page 4/208

1 Introduction
This document provides information on STM32MP23xA/D devices, such as description, functional overview, pin
assignment and definition, electrical characteristics, packaging and ordering information.
It must be read in conjunction with the STM32MP23/25xx reference manual (RM0457).
For information on the device errata with respect to the datasheet and reference manual, refer to the
STM32MP23xx/25xx device errata (ES0598).
For information on the Arm
®
Cortex
®
- M33 core, refer to the Cortex
®
- M33 Technical Reference Manual, available
from the www.arm.com website.
Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
STM32MP231A/D STM32MP233A/D STM32MP235A/D
Introduction
DS14635 - Rev 3
page 5/208
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